期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 58, 期 7, 页码 1892-1897出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2011.2142417
关键词
Electrical initialization; etch-through-spacer (ETS) technique; layer selection; 3-D memory
资金
- Ministry of Knowledge Economy/Korea Evaluation Institute of Industrial Technology (MKE/KEIT) [10035320]
- Korea Evaluation Institute of Industrial Technology (KEIT) [10035320] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
A novel electrical layer-selection method in a bit-line stacked 3-D NAND memory array is proposed. The stacked layers are selected by using multiple source select lines with erased cells in a layer. The operation scheme and simulation results for the electrical layer selection are discussed. An etch-through-spacer technique is developed to form a terraced body for a vertical contact process.
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