4.6 Article

Comprehensive Investigation of Statistical Effects in Nitride Memories-Part I: Physics-Based Modeling

期刊

IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 57, 期 9, 页码 2116-2123

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2010.2054472

关键词

Atomistic doping; nitride memories; semiconductor device modeling; SONOS memories; TANOS memories

资金

  1. European Commission [214431]

向作者/读者索取更多资源

This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.

作者

我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。

评论

主要评分

4.6
评分不足

次要评分

新颖性
-
重要性
-
科学严谨性
-
评价这篇论文

推荐

Article Engineering, Electrical & Electronic

Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators

A. Parisi, F. Tesolin, M. Mercandelli, L. Bertulessi, A. L. Lacaita

Summary: This study introduces a compact self-biasing dynamic startup circuit for class-C voltage-controlled oscillators, achieving excellent startup time and extremely small area.

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS (2021)

Article Engineering, Electrical & Electronic

A Generalization of the Groszkowski's Result in Differential Oscillator Topologies

Francesco Buccoleri, Andrea Bonfanti, Andrea L. Lacaita

Summary: This paper presents novel equations to describe the dependence of oscillation frequency on harmonic content in differential oscillators, rigorously considering the effect of common-mode oscillation. The inclusion of an additional term related to transistor current on drain voltage is disclosed for the first time, showing dominance in ohmic operation. Results obtained from applying this framework to Van der Pol oscillators in 28-nm bulk CMOS technology match well with detailed circuit simulations. The analysis reveals that the classical theory may not account for close-in phase noise performance when even harmonics are relevant, while the novel theoretical framework justifies the simulation results and explores new mechanisms of flicker noise up-conversion in the considered oscillator structures.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2021)

Article Engineering, Electrical & Electronic

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino

Summary: This article introduces a novel fractional-N sampling type-I phase-locked loop (PLL) with digital phase error correction (DPEC) and frequency locking method, which provides low jitter performance, fast lock, low spurs, and power consumption, while occupying a small area.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2022)

Article Engineering, Electrical & Electronic

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise

Luca Bertulessi, Dmytro Cherniak, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Summary: This paper presents a novel technique to reduce locking time in a Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD), improving the trade-off between phase noise and locking time. The implemented CMOS fractional-N frequency synthesizer demonstrates low output signal spot noise and a fast locking time, overcoming limitations and cycle slips associated with 1-bit phase detector PLLs.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2022)

Article Engineering, Electrical & Electronic

Random Telegraph Noise Intensification After High-Temperature Phases in 3-D NAND Flash Arrays

Gerardo Malavena, Mattia Giulianini, Luca Chiavarone, Alessandro S. Spinelli, Christian Monzio Compagnoni

Summary: In this research, it is shown through experiments that a high-temperature idle/data-retention phase leads to a permanent intensification of random telegraph noise (RTN) in 3-D NAND Flash arrays. The effect is explained by the depassivation of traps at grain boundaries during the high-temperature phase, resulting in nonuniformities in channel inversion and an increased number of active defects in the RTN process.

IEEE ELECTRON DEVICE LETTERS (2022)

Article Engineering, Electrical & Electronic

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology

Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino

Summary: This study analyzes harmonic generation in ring-based injection-locked frequency dividers, presenting a novel divide-by-five ILFD that significantly broadens locking range through reinforced multi-injection. The implemented stage operates over a wide frequency range with good power consumption efficiency, achieving the highest operating frequency among current CMOS ILFDs.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2022)

Article Engineering, Electrical & Electronic

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino

Summary: This work introduces a new bang-bang fractional-N phase-locked loop with quantization noise shaping that overcomes the noise limit of a standard phase detector. An adaptive algorithm ensures optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, achieves low jitter power consumption and high performance in different channel configurations.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2022)

Article Physics, Applied

Modeling of ferroelectric tunnel junctions based on the Pt/BaTiO3/Nb:SrTiO3 stack

M. Dossena, G. Malavena, A. S. Spinelli, C. Monzio Compagnoni

Summary: This paper presents a comprehensive modeling investigation of the Pt/BaTiO3/Nb:SrTiO3 stack designed as a Ferroelectric Tunnel Junction (FTJ), with a focus on specific material features often overlooked. The analysis includes validation through a consistent comparison with experimental data, exploring the resistive memory window of the FTJ, and providing insights for the development of next-generation memory technologies based on FTJ.

JOURNAL OF APPLIED PHYSICS (2022)

Article Engineering, Electrical & Electronic

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

Gabriele Be, Angelo Parisi, Luca Bertulessi, Luca Ricci, Lorenzo Scaletti, Mario Mercandelli, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti

Summary: This paper presents a 12-bit SAR-based TI-ADC with a fully programmable interleaving factor, achieving low interleaving spurs and high SNDR at different configurations. The ADC demonstrates good performance metrics and low power dissipation at 900MS/s.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2022)

Article Engineering, Electrical & Electronic

Phase Noise Analysis of Periodically ON/OFF Switched Oscillators

Giacomo Castoro, Simone M. Dartizio, Andrea L. Lacaita, Salvatore Levantino

Summary: The paper provides a detailed analysis of phase noise in periodically switched oscillators (PSOs) and shows that their output phase noise cannot be estimated using the analogy to retimed oscillators. The authors derive closed form expressions for the transfer of both the reference and the oscillator noise, including a correction for the contribution of the oscillator close-in phase noise. The results are validated through simulations and the excess noise arising from the on-off transients is also discussed.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2023)

Article Engineering, Electrical & Electronic

Time Dynamics of the Down-Coupling Phenomenon in 3-D NAND Strings

Mattia Giulianini, Gerardo Malavena, Christian Monzio Compagnoni, Alessandro S. Spinelli

Summary: This paper presents a detailed analysis of the time dynamics of the down-coupling phenomenon (DCP) in 3-D NAND Flash memory strings. The transient time dynamics of the channel potential following the wordline (WL) bias transition from the pass voltage to zero is studied via numerical simulation. The results highlight the existence of three temporal regimes controlled by different physical processes and can be used as a design guideline for NAND strings.

IEEE TRANSACTIONS ON ELECTRON DEVICES (2022)

Article Engineering, Electrical & Electronic

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

Francesco Tesolin, Simone M. Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Summary: An LO phase-shifting system based on digital fractional -N bang-bang phase-locked loops (PLLs) in the 8.5-10.0-GHz range is presented. The system leverages a direct phase modulation method to perform LO phase-shifting within the frequency synthesizer, achieving inherently linear phase-shifting characteristic. The synchronization between fractional -N PLL cores is achieved by clocking with the same reference clock.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2023)

Article Engineering, Electrical & Electronic

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Summary: This work presents a solution for a low-spur and low-jitter fractional-N digital phase-locked loop (PLL). The use of an inverse-constant-slope DTC and a frequency-control-word subtractive dithering technique effectively reduces the fractional spurs caused by non-linearity and improves system performance.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2023)

Proceedings Paper Engineering, Electrical & Electronic

Investigation of the Statistical Spread of the Time-Dependent Dielectric Breakdown in Polymeric Dielectrics for Galvanic Isolation

G. Malavena, J. L. Mazzola, M. Greatti, C. Monzio Compagnoni, A. L. Lacaita, V Marano, M. Lauria, D. Paci, E. Speroni, A. S. Spinelli

Summary: This study investigates the statistical spread of Time-Dependent Dielectric Breakdown (TDDB) in thick polymeric dielectrics for galvanic isolation devices. By conducting Monte Carlo simulations and introducing inhomogeneities in the material properties, the experimental TDDB spread is successfully reproduced. The findings of this study have important implications for the design and use of galvanic isolation devices.

2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC) (2022)

Proceedings Paper Engineering, Electrical & Electronic

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity

Angelo Parisi, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita

Summary: The novel technique utilizes numerical Phase-Locked Loops (NPLLs) to autonomously generate a distortion-less replica of the input signal and adaptively estimate polynomial correction via filters, significantly improving ADC performance.

2021 28TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (IEEE ICECS 2021) (2021)

暂无数据