Article
Engineering, Electrical & Electronic
Xavier Aragones, Enrique Barajas, Albert Crespo-Yepes, Diego Mateo, Rosana Rodriguez, Javier Martin-Martinez, Montserrat Nafria
Summary: The article presents an extensive experimental analysis of the aging effects on RF linear power amplifiers due to HCI and BTI, with two different PA topologies implemented in a CMOS 65-nm technology. The study shows that the reduced transistor degradation in CR PA results in higher robustness in RF parameters compared with CS PA circuit.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
(2021)
Article
Computer Science, Hardware & Architecture
L. Zohar, I. Shternberg, B. Khamaisi, A. Nazimov, A. Ben-Bassat, O. Degani
Summary: This letter describes the reliability characterization process of a switched capacitor digital power amplifier (SCDPA) manufactured in CMOS acrlong 16FF technology. It explains the design analysis, stress experiments, and the novel solution to overcome NBTI and second harmonics degradation issues.
IEEE SOLID-STATE CIRCUITS LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Wei-Chun Hung, Yu-Fa Tu, Ting-Chang Chang, Mao-Chou Tai, Kuan-Hsu Chen, Fu-Yuan Jin, Chien-Hung Yeh, Wei-Chieh Hung, Chin-Han Chang, Hung-Ming Kuo, Chen-Hsin Lien
Summary: This work explores the issue of abnormal two-stage hot carrier injection (HCI) degradation in n-type lateral double-diffused MOS (LDMOS) transistors. The degradation mechanism consists of two stages: electron injection into the interface layer (IL) caused by impact ionization under the contact field plate (CFP), and positive bias temperature instability (PBTI) effects caused by Joule heating. Temperature variation experiments and TCAD simulations have shown that HCI can lead to severe PBTI effects and device degradation.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Review
Computer Science, Information Systems
Jian Fu Zhang, Rui Gao, Meng Duan, Zhigang Ji, Weidong Zhang, John Marsland
Summary: This paper discusses the impact of device aging on chip design in CMOS technology. The focus is on the study of negative and positive bias temperature instabilities (NBTI and PBTI) and proposes a new As-grown-Generation (AG) model for predicting long-term BTI at low biases.
Article
Engineering, Electrical & Electronic
Xhesila Xhafa, Ali Dogus Gungordu, Didem Erol, Yavuzhan Yavuz, Mustafa Berke Yelten
Summary: This article discusses a test chip design in 40-nm process technology to characterize the degradation in MOSFETs caused by time-based factors. Results show that BTI and HCI affect transistor performance, with body effect and poststress variations significantly impacting both transistor and circuit performance.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
(2021)
Article
Engineering, Electrical & Electronic
Yongkang Xue, Pengpeng Ren, Junjie Wu, Zhuyou Liu, Shuying Wang, Yu Li, Zirui Wang, Zixuan Sun, Da Wang, Yichen Wen, Shiyu Xia, Lining Zhang, Jianfu Zhang, Zhigang Ji, Junwei Luo, Huixiong Deng, Runsheng Wang, Lianfeng Yang, Ru Huang
Summary: A complete separation flow for different types of traps is achieved, allowing the modeling and characterization of different traps separately by simple experiments. A unified aging prediction framework is proposed by modeling each type of trap respectively and its long-term predictive capability is experimentally verified under various working conditions. The contribution of each trap to degradation is discussed, which is helpful for Design-Technology co-optimization (DTCO) in advanced nodes.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Longda Zhou, Qingzhu Zhang, Hong Yang, Zhigang Ji, Guilei Wang, Qianqian Liu, Bo Tang, Rui Gao, Eddy Simoen, Huaxiang Yin, Chao Zhao, Anyan Du, Jun Luo, Wenwu Wang
Summary: This experimental study observed an immediate recovery of generated interface traps (N-IT) in Si p-FinFETs within a recovery time of 400 μs, which is attributed to the accumulation of hydrogen atoms. Additionally, the widely reported delayed recovery after Mode-B ac stress is observed when the accumulated hydrogen atoms in a pulse-on phase are quickly consumed in the following pulse-off phase.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Wei-Chun Hung, Jia-Hong Lin, Ting-Chang Chang, Yu-Zhe Zheng, Yang-Hao Hung, Yu-An Chen, Li-Wen Wang, Chia-Hung Tsai, Simon Ogier
Summary: This study investigates the impact of source-drain-gate electrode overlap geometry on the reliability of organic thin-film transistors (OTFTs). The degradation of electrical characteristics after stress-induced hot carrier instability (HCI) is analyzed by comparing I-D-V-G transfer curves and C-V characteristic curves before and after the stress test. Severe degradation is observed in standard symmetry and source-extended structures, but increased reliability is observed in a drain-extended structure. A physical model is proposed to explain this behavior, and Technology Computer-Aided Design (TCAD) simulations are used for further understanding of the electrical field distribution in the devices.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Youngmin Kim, Junghwan Han, Jae-Seung Lee, Taehwan Jin, Pilsung Jang, Heeseon Shin, Jongwoo Lee, Thomas Byunghak Cho
Summary: This article discusses power-efficient RF receiver designs for advanced LTE cellular applications, which can support multiple-channel RF signals with flexibility in various CMOS technologies. Different LNA topologies are used to achieve different bandwidth handling capabilities and linearity requirements.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
(2021)
Article
Engineering, Electrical & Electronic
Xuewei Ding, Guofu Niu, Huilong Zhang, Weike Wang, Kimihiko Imura, Fa Foster Dai
Summary: Hot carrier reliability is measured and modeled on 14/16-nm FinFETs used for RF PAs under nonconducting (NC) RF and dc stresses. The impact of stress on I - V and RF parameters is examined, revealing that degradations are located near the drain end of the channel within the pinch-off region. Measurement-based lifetime modeling is necessary as the quasi static-approximation (QSA) significantly underestimates degradation for classic V-gs = 0 V OFF-state RF stress. Die-to-die variations dominated by variations of the subthreshold channel current are observed at near-threshold V-gs, and the modeling shows that the near-threshold RF stress is approximately quasi-static. These FinFETs provide sufficient margins against NC RF stress for intended PA applications.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Bin Ye, Yi Gu, Hang Xu, Chengkang Tang, Hao Zhu, Qingqing Sun, David Wei Zhang
Summary: This study demonstrates an experimental approach to mitigate the negative bias temperature instability (NBTI) in 14-nm FinFET devices through HKMG thermal processing optimization. The NBTI reliability degradation is found to be caused by the formation of defective SiO ₂ interlayer and interface traps. The optimized post-dielectric and post-Si-cap annealing processes successfully achieve an improved balance between SiO ₂ interlayer quality and high-k/SiO ₂ interface trap density, effectively suppressing NBTI-induced device variations.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Computer Science, Hardware & Architecture
Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
Summary: A static timing analysis methodology based on an effective current source model (ECSM) is proposed for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter. The methodology utilizes device-level variation aware timing models to represent threshold-crossing points in an ECSM.libs file. A python-based tool is developed to estimate the path-level timing performance in pre-and post-stress conditions. The proposed model reduces the number of SPICE/Stress simulations by 98.13% compared to previous simulation-based techniques.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Nanoscience & Nanotechnology
Yajin Dong, Jiaxiang Li, Wenyue Liang, Xianghong Nan, Long Wen, Qin Chen
Summary: Copper-silicon heterojunctions show higher responsivity and longer cutoff wavelength compared to gold-silicon heterojunctions in the sub-bandgap wavelength range of silicon. The advanced photodetection performance of copper-silicon devices is attributed to the relatively higher electron density of state above the Fermi level and the higher ejection probability.
Article
Engineering, Electrical & Electronic
Xianghui Li, Chengkang Tang, Yi Gu, Xin Chao, Chen Wang, Hao Zhu, Qingqing Sun, David Wei Zhang
Summary: In this study, the relationship between interface and oxide traps and body-biased hot carrier degradation (HCD) in 14 nm nFinFETs is investigated. It is observed that the device performance degradation accelerates as the body bias voltage increases. Particularly, the interface traps exhibit a rapid response even at low body bias levels, while the oxide traps only increase above a certain body bias threshold. The location and characteristics of the newly generated traps are analyzed, and a comprehensive analysis of the corresponding carrier transportation mechanism is built based on the trap location.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Materials Science, Multidisciplinary
Jiayang Zhang, Zirui Wang, Runsheng Wang, Zixuan Sun, Ru Huang
Summary: This article experimentally studies the influence of body bias dependence on the bias temperature instability (BTI) in bulk FinFETs, under different test conditions for the first time. It is observed that contrary to the traditional understanding, body bias actually has a non-negligible impact on BTI degradation in FinFETs, and a forward body bias (FBB) can reduce the BTI degradation, which is opposite to the trend in planar devices. These findings are important for understanding and modeling reliability in FinFETs.
ENERGY & ENVIRONMENTAL MATERIALS
(2022)
Article
Materials Science, Coatings & Films
Jurriaan Schmitz
SURFACE & COATINGS TECHNOLOGY
(2018)
Article
Materials Science, Multidisciplinary
Mengdi Yang, Antonius A. I. Aarnink, Jurriaan Schmitz, Alexey Y. Kovalgin
Article
Engineering, Electrical & Electronic
Vidhu Puliyankot, Giulia Piccolo, Raymond J. E. Hueting, Jurriaan Schmitz
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2018)
Article
Physics, Applied
Gaurav Gupta, Sourish Banerjee, Satadal Dutta, Antonius A. I. Aarnink, Jurriaan Schmitz, Alexey Y. Kovalgin, Raymond J. E. Hueting
JOURNAL OF APPLIED PHYSICS
(2018)
Article
Engineering, Electrical & Electronic
Maurits J. de Jong, Cora Salm, Jurriaan Schmitz
MICROELECTRONICS RELIABILITY
(2018)
Article
Materials Science, Multidisciplinary
Arnoud J. Onnink, Jurriaan Schmit, Alexey Y. Kovalgin
Article
Engineering, Electrical & Electronic
Maurits J. de Jong, Cora Salm, Jurriaan Schmitz
MICROELECTRONICS RELIABILITY
(2019)
Article
Engineering, Electrical & Electronic
Milou van Rijnbach, Raymond J. E. Hueting, Maciej Stodolny, Gaby Janssen, Jimmy Melskens, Jurriaan Schmitz
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2020)
Article
Engineering, Manufacturing
Kees van der Zouw, Antonius A. I. Aarnink, Jurriaan Schmitz, Alexey Y. Kovalgin
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
(2020)
Article
Engineering, Electrical & Electronic
Matthias L. Vermeer, Raymond J. E. Hueting, Luca Pirro, Jan Hoentschel, Jurriaan Schmitz
Summary: Quantification of interface traps in double-gate fully depleted silicon-on-insulator transistors is crucial for accurate device modeling and technology development. A new method combining the g(m)/I-D method and a revised form of the k-sweep method was developed in this study, resulting in a typical trap density of 2*10^(11)cm^(-2)eV^(-1). However, the allocation of traps to the front or back interface is challenging, with at least a 20% error reported.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Review
Green & Sustainable Science & Technology
Pelin Yilmaz, Jurriaan Schmitz, Mirjam Theelen
Summary: This review paper provides an overview of studies on Potential Induced Degradation (PID) in copper indium gallium diselenide (CIGS) photovoltaics, including observations, proposed origins, testing methods, and preventive measures. Studies on cells, minimodules, and modules are presented and compared.
RENEWABLE & SUSTAINABLE ENERGY REVIEWS
(2022)
Review
Green & Sustainable Science & Technology
M. Aghaei, A. Fairbrother, A. Gok, S. Ahmad, S. Kazim, K. Lobato, G. Oreski, A. Reinders, J. Schmitz, M. Theelen, P. Yilmaz, J. Kettle
Summary: This article reviews the latest knowledge on the reliability of PV modules, including reliability metrics, stress factors, degradation, and failure modes. By analyzing the degradation and failure phenomena, strategies can be developed to improve the operational lifetime of PV systems and reduce the cost of electricity.
RENEWABLE & SUSTAINABLE ENERGY REVIEWS
(2022)
Review
Energy & Fuels
Bas van Wijngaarden, Junchun Yang, Jurriaan Schmitz
Summary: This paper reviews literature published from 2017 to 2021 on the Cox-Strack method for contact resistivity determination in photovoltaic cell engineering. It analyzes possible inaccuracies in the method and suggests that more than half of the reviewed articles may require additional analysis for accurate quantification of lower contact resistance values. The paper concludes with recommendations for improving the Cox-Strack methodology.
SOLAR ENERGY MATERIALS AND SOLAR CELLS
(2022)
Proceedings Paper
Engineering, Electrical & Electronic
Emre Ozturk, Mike J. Dikkers, Kevin M. Batenburg, Cora Salm, Jurriaan Schmitz
2019 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW)
(2019)
Proceedings Paper
Engineering, Electrical & Electronic
Kees van der Zouw, Antonius A. I. Aarnink, Jurriaan Schmitz, Alexey Y. Kovalgin
2019 IEEE 32ND INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS)
(2019)