Combined Nanoscale and Device-Level Degradation Analysis of $\hbox{SiO}_{2}$ Layers of MOS Nonvolatile Memory Devices

出版年份 2009 全文链接

标题

作者

关键词

出版物

Volume 9, Issue 4, Pages 529-536

出版商

Institute of Electrical and Electronics Engineers (IEEE)

发表日期

2009-07-16

DOI

10.1109/tdmr.2009.2027228

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