A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation

This paper presents a successive approximation (SA) algorithm called LSB-first SA and a corresponding 10 bit ADC implementation. The energy per conversion and number of bitcycles per conversion used by this algorithm both scale logarithmically with the activity of the input signal, such that an N-bit conversion uses between 2 and 2N+1 bitcycles, compared to N for conventional binary SA. This algorithm reduces ADC power consumption when sampling signals with low mean activity. The ADC is implemented in a 0.18 mu m CMOS process. With a 0.6 V supply, the maximum sample rate, leakage power, and ENOB are 16 kHz, 0.58 nW, and 9.73 b, averaged over 10 test chips. The DNL and INL are bounded at 0.09 and 0.22 LSBs. Given a DC input, the ADC achieves its best-case FoM of 3.5 fJ/conversion-step. Given a fullscale Nyquist sinusoid input, the ADC has its worst-case FoM of 20 fJ/conversion-step. The supply voltage can be increased to 1.0 V to reach a sample rate of 450 kHz, or decreased to 0.5 V to achieve a 2.9-17 fJ/conversion-step FoM range.