期刊
IEEE ELECTRON DEVICE LETTERS
卷 32, 期 3, 页码 393-395出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2010.2099203
关键词
Closed-form expressions; parasitic resistance and inductance; through-silicon vias (TSVs)
资金
- National S&T Major Project of China [2009ZX03006-001-01]
- National Basic Research Program of China (973 Program) [2010CB732606]
In this letter, closed-form expressions are proposed to calculate the parasitic resistance and inductance of different profiles of through-silicon vias (TSVs). The formulas for the tapered TSV are developed as the functions of the geometric parameters of the via. The expressions also cover the straight TSV when the slope wall angle is zero. The comparison between the formulas and numerical electromagnetic results shows that the formulas have high accuracy at low frequency, with maximum errors of 2% and 5% for the resistance and the inductance, respectively. The errors increase at high frequencies due to the skin effect and can be minimized by using fitting parameters.
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