The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse

(2019) Ismael Seidel et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator

(2018) Wagner Penny et al.   Journal of Real-Time Image Processing

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

(2017) Bianca Silveira et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture

(2016) Cláudio Machado Diniz et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

(2015) Gang He et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A multiplierless pruned DCT-like transformation for image and video compression that requires ten additions only

(2015) Vítor A. Coutinho et al.   Journal of Real-Time Image Processing

A Multitransform Architecture for H.264/AVC High-Profile Coders

(2010) Woong Hwangbo et al.   IEEE TRANSACTIONS ON MULTIMEDIA

A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder

(2009) Yu-Kun Lin et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY

A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation

(2009) Chao-Yang Kao et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS